The present invention relates to semiconductor computer memories. In particular it relates to erasable programmable read only memories (EPROMs).
EPROMs are now well known semiconductor devices, often formed using MOS technology. AMOS EPROM cell is shown in FIG. 1 with word line 14 coupled to bit line 16 by a MOS transistor 34. Bit line 16 serves as a drain for transistor 34, and line 17 serves as a source. Transistor 34 includes a floating gate 35, electrically isolated from the control gate 37. The transistor is programmed by electrons flowing onto the floating gate and being trapped there. This causes the floating gate to act as a capacitor holding charge, thereby altering the functionality of the transistor in a detectable manner, e.g. changing its threshold voltage. In one type of cell, the programming is done by bringing both the word and bit lines high.
The MOS memory cell of FIG. 1 operates at TTL voltage levels or in the general vicinity, but has the advantage of being erasable. It can be erased, for example, by removing the charge from the floating gate using ultraviolet light or electrical techniques. Thus, a cell can be programmed and verified, then erased and reprogrammed if necessary. The capability of reprogramming eliminates the need for test cells as in bipolar PROM circuits.
A typical MOS EPROM circuit is shown in FIG. 2A. As shown, the circuit uses an array 43 of the cells of FIG. 1 with an input pin 36, input buffer 38 and decode circuit 40 for each word line 41. Each memory cell 42 is also connected to a sense line 47, which is coupled to a sense circuit 44, output buffer 46 and output node 48. To program a memory cell 42 of FIG. 2A, a program voltage is provided on a Vpp node 39 to address decode circuit 40 to the selected word line 41. Vpp node 39 not only supplies the high voltage needed for programming, but also selects the programming mode when asserted by enabling programming circuit 45. For most EPROMs Vpp is about 2.5 times the read voltage, which is generally around 5 volts but may be smaller.
Any cell connected to a high word line and a sense line at a high value will be programmed. An input provided through output node 48 and programming circuit 45 causes sense line 47 to carry a high value. Thus, this circuit requires a programming circuit coupled to the output pin, just as the bipolar PROM requires a programming circuit. However, the separate high current data input circuitry coupled to the output (or combined circuitry with high current capability) is eliminated. During a read operation, read voltage levels are used to select the word line through input buffer 38 and decode circuit 40 with the bit lines being sensed through sense circuit 44 and output buffer 46.
EPROM transistor arrays are typically arranged in one of two types of configurations. The older, more prevalent type is the "T" cell, shown in FIG. 2B. Each transistor 34' in this arrangement has a unique drain column, or bit line, 16' and word line 14' combination. The sources 17 are usually attached to a common node throughout the array.
On the other hand, in the shared column or virtual ground array configuration shown in FIG. 2C, pairs of transistors along word line 14" share coincident drain column 16" connections and adjacent pairs share coincident source column 17" connections. This configuration therefore requires selection of word, drain and source to uniquely select an EPROM transistor. Although the shared column approach usually produces a denser array, the read and programming accesses are more difficult since unselected transistors adjacent to the selected one are easier to inadvertently sense or disturb.
A standard method for programming a shared column EPROM is to force the V.sub.ss source voltage and V.sub.pd drain programming voltage on the respective selected source and drain columns. All other columns are allowed to float. At the same time, the V.sub.pp gate programming voltage is applied to the XS.sub.i row select line. FIG. 3 shows a group of EPROM memory cells used to explain the programming process and certain problems with its column selection process. If transistor memory cell 25 is to be programmed, the source and drain columns are selected by asserting YSS.sub.1 and YSD.sub.1, which turns on the transistors coupled to lines 11 and 13, connecting them to drain line D.sub.k 50 at V.sub.pd and source line S.sub.k 60 at V.sub.ss, respectively. All other transistors and, more importantly, column RMOS III lines float. Unfortunately, this process can lead to errors in adjacent cells, through an effect known as disturb. This problem may occur when a transistor 25, which is desired to be programmed, is adjacent to a transistor 27 which is in an unprogrammed state and is intended to stay that way. As transistor 25 is programmed, the source column 9 of adjacent memory transistor 27 may be floating at voltage V.sub.ss. With line 11 carrying the programming voltage V.sub.pd, there will be a voltage drop across transistor 27. Because word select line XS.sub.i selects all the gates on the entire row, transistor 27 will conduct current. The parasitic capacitance C.sub.col of source column 9 will require a finite time to rise to V.sub.pd, during which current will conduct through transistor 27. The current may be at a high enough level to inject hot electrons into the floating gate of memory transistor 27; from this the floating gate would charge to a negative voltage. Although a single such event is probably insufficient to change its data value, repeated cycles can place sufficient charge on the floating gate of transistor 27 to corrupt its data value. This is a significant disadvantage of prior art EPROMs.